1. Technical Field
Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time.
2. Related Art
In general, a semiconductor memory device including double data rate synchronous DRAM (DDR SDRAM) includes a very large number of memory cells. The integration degree of semiconductor memory devices is increased according to the development of a process technology, and thus the number of memory cells is further increased. If any one of such memory cells fails, a semiconductor memory device including the fail memory cell must be discharged because it does not perform a required operation.
As the process technology of the semiconductor memory device advances, defects occur in only some memory cells. It is very inefficient to discard the entire semiconductor memory device due to these failed memory cells when considering the yield of products.
Accordingly, in order to supplement such failed memory cells, redundancy memory cells are also included in a semiconductor memory device in addition to the normal memory cells.
A redundancy memory cell is a circuit for repairing failed memory (hereinafter referred to as a “target repair memory cell”) if a failure occurs in a normal memory cell.
More specifically, for example, with a read or write operation, when a target repair memory cell is accessed, a normal memory cell not the target repair memory cell is internally accessed. In this case, the accessed normal memory cell is a redundancy memory cell.
Accordingly, when an address corresponding to a target repair memory cell is received, a semiconductor memory device performs an operation for accessing a redundancy memory cell other than the target repair memory cell (hereinafter referred to as a “repair operation”). A normal operation is guaranteed for the semiconductor memory device through such a repair operation.